1. Field of the Invention
The present invention relates to a power semiconductor device and a method of manufacturing the same. More particularly, the invention relates to a power semiconductor device for use in an inverter and a method of manufacturing the same.
2. Description of the Background Art
In recent years, motors have gone inverter-driven, for example, in the field of air conditioning in terms of energy saving, and an increasing number of power semiconductor devices for inverters have been produced.
There is an increasing need for such power semiconductor devices not only to reduce power dissipation but also to reduce size and costs in terms of space saving.
A background art power semiconductor device is described below with reference to FIGS. 38 through 43. FIG. 38 is a circuit diagram of a three-phase inverter IV.
As illustrated in FIG. 38, the three-phase inverter IV comprises three inverters IV1 to IV3. The inverter IV1 includes IGBTs (insulated gate bipolar transistors, which are in some cases referred to simply as transistors hereinafter) Q1L and Q1U connected in series between a power supply line P providing a power supply voltage VDD and a power supply line N connected to a ground potential, and free wheeling diodes D1L and D1U connected in inverse-parallel with the transistors Q1L and Q1U, respectively. A connection node between the transistors Q1L and Q1U is connected to a first end of a load LU.
The inverter IV2 is similar in construction to the inverter IV1. Specifically, the inverter IV2 includes transistors Q2L and Q2U connected in series between the power supply lines P and N, and free wheeling diodes D2L and D2U connected in inverse-parallel with the transistors Q2L and Q2U, respectively. A connection node between the transistors Q2L and Q2U is connected to a first end of a load LW.
Likewise, the inverter IV3 includes transistors Q3L and Q3U connected in series between the power supply lines P and N, and free wheeling diodes D3L and D3U connected in inverse-parallel with the transistors Q3L and Q3U, respectively. A connection node between the transistors Q3L and Q3U is connected to a first end of a load LV. The loads LU, LV and LW have respective second ends connected together.
In part of the inverter IV1 shown in FIG. 38 which is comprised of the transistor Q1L and the diode D1L, the reference characters E, C and G designate the emitter, collector and gate terminals of the transistor Q1L, respectively. The diode D1L has an anode terminal connected to the emitter terminal E and a cathode terminal connected to the collector terminal C.
A cross-sectional structure of the transistor Q1L and the diode D1L is described with reference to FIG. 39. In the description below, it is assumed that the transistor Q1L is of an n-channel type and the diode D1L is a diode having a p-type anode formed on an n-type semiconductor substrate.
As illustrated in FIG. 39, the transistor Q1L includes a p-type base region 8 formed in an upper main surface of an n-type silicon substrate 1T, and a plurality of trench-type gate electrodes 11 arranged in parallel and each extending through the p-type base region 8 in the direction of the depth thereof. A plurality of p-type semiconductor regions 12 containing a p-type impurity of a relatively high concentration are selectively formed in the surface of the p-type base region 8 in such a manner that each lies between adjacent two of the gate electrodes 11. The p-type semiconductor regions 12 are provided for the purpose of making a satisfactory electric connection between the p-type base region 8 and emitter electrodes 19.
A plurality of n-type emitter regions 9 containing an n-type impurity of a relatively high concentration are formed on the opposite sides of the respective p-type semiconductor regions 12. The n-type emitter regions 9 are designed to contact respective gate insulation films (not shown) formed on the surface of the gate electrodes 11. The silicon substrate 1T serves herein as an n-type base layer of the IGBT.
The emitter electrodes 19 formed partially on the surface of the n-type emitter regions 9 are electrically connected to the emitter terminal E. The gate electrodes 11 are electrically connected to the gate terminal G. A plurality of parallel-connected IGBT structures constitute the transistor Q1L. A region in which the p-type base region 8, the n-type emitter regions 9 and the gate electrodes 11 are formed is referred to hereinafter as a cell region 2TC.
A plurality of p-type semiconductor regions 28 at a floating potential are arranged concentrically so as to surround the cell region 2TC, to define an electric field relieving ring region 2TG. The structure of the cell region 2TC and the electric field relieving ring region 2TG is generically referred to as an emitter-side structure 2.
An n-type buffer layer 3a is formed on a lower main surface of the silicon substrate 1T. A p-type collector layer 4 is formed on the surface of the n-type buffer layer 3a, and a collector electrode 5a of metal is formed on the surface of the p-type collector layer 4.
FIG. 40 is a plan view of the transistor Q1L as viewed from above the emitter electrode. As illustrated in FIG. 40, the transistor Q1L is formed on a rectangular board, and is configured such that the rectangular electric field relieving ring region 2TG surrounds the rectangular cell region 2TC. An n-type semiconductor region 27 at a floating potential is formed to surround the electric field relieving ring region 2TG.
In the cell region 2TC, a plurality of gate lines GL are arranged in parallel, and are connected at their respective ends to a gate ring region GR defining the outer periphery of the cell region 2TC. All of the gate lines GL are at a common potential. A gate pad GP is partially provided for electric connection between the gate lines GL and the exterior.
The spaces between the gate lines GL are covered with the emitter electrodes 19, and an upper emitter electrode 190 for making electric connections between the emitter electrodes 19 covers the emitter electrodes 19. For purposes of illustration, the upper emitter electrode 190 is shown with parts broken away in FIG. 40.
The cross-section of the transistor Q1L shown in FIG. 39 is a cross-section taken along the line Axe2x80x94A of FIG. 40. The gate electrodes 11 shown in FIG. 39 are only some of a plurality of gate electrodes 11 arranged longitudinally of the gate lines GL and each extending perpendicularly to the length of the gate lines GL.
Referring again to FIG. 39, the diode D1L includes a p-type anode layer 29 formed in an upper main surface of an n-type silicon substrate 1D. A anode electrode not shown is formed on the surface of the anode layer 29, and is electrically connected to the emitter terminal E. A region in which the anode layer 29 and the anode electrode are formed is referred to as an anode region 2DA.
A plurality of p-type semiconductor regions 28 at a floating potential are arranged concentrically so as to surround the anode region 2DA, to define an electric field relieving ring region 2DG. The structure of the anode region 2DA and the electric field relieving ring region 2DG is generically referred to as an anode-side structure 2D.
An n-type buffer layer 3b is formed on a lower main surface of the silicon substrate ID. An n-type semiconductor layer 6 containing an n-type impurity of a relatively high concentration is formed on the surface of the n-type buffer layer 3b, and a cathode electrode 5b of metal is formed on the surface of the n-type semiconductor layer 6. The cathode electrode 5b is electrically connected to the collector terminal C.
The n-type semiconductor layer 6 is a layer for providing an ohmic contact between the cathode electrode 5b and the n-type buffer layer 3b. The silicon substrate ID is a layer corresponding to an xe2x80x9cixe2x80x9d (intrinsic) layer of the pin diode.
FIG. 41 is a plan view of the diode D1L as viewed form above the anode electrode. As illustrated in FIG. 41, the diode D1L is formed on a rectangular board, and is configured such that the rectangular electric field relieving ring region 2DG surrounds the rectangular anode region 2DA. An n-type semiconductor region 27 at a floating potential is formed to surround the electric field relieving ring region 2DG.
The cross-section of the diode D1L shown in FIG. 39 is a cross-section taken along the line Bxe2x80x94B of FIG. 41. The anode layer 29 shown in FIG. 39 is only part of the actual anode layer 29.
As stated above, an arrangement having two devices arranged in parallel, i.e., the IGBT and the free wheeling diode which are formed separately has been employed to provide the three-phase inverter IV. Such an arrangement is disadvantageous in the increased module area of the three-phase inverter.
To overcome the disadvantage, an arrangement has been developed in which a free wheeling diode is incorporated in an IGBT. The arrangement in which the free wheeling diode is incorporated in the IGBT is discussed below with reference to FIGS. 42 and 43.
FIG. 42 is a cross-sectional view of an IGBT 90 with a free wheeling diode incorporated therein. The IGBT 90 is similar in basic construction to the transistor Q1L described with reference to FIG. 39. Like reference characters are used to designate parts identical with those of FIG. 39, and a repetition of description will be avoided. An emitter-side structure 2 shown in FIG. 42 corresponds to the emitter-side structure 2 of FIG. 39, and both of them are substantially identical. The silicon substrate 1T shown in FIG. 39 is referred to hereinafter as an n-type base layer 1.
The IGBT 90 includes an n-type buffer layer 3; a p-type collector layer 4 selectively formed in a main surface of the n-type buffer layer 3 in corresponding relation to a region in which the p-type base region 8 is formed (i.e., the cell region 2TC shown in FIG. 39); an n-type cathode region 6 selectively formed so as to surround the p-type collector layer 4 in spaced apart relation to the p-type collector layer 4; and a collector electrode 5 of metal in contact with the n-type buffer layer 3, the p-type collector layer 4 and the n-type cathode region 6.
Two current paths (a) and (b) shown in FIG. 42 are described in detail with reference to FIG. 43.
FIG. 43 shows part of the plurality of IGBT structures which includes two gate electrodes 11. The gate insulation films 10 which are not shown in FIGS. 39 and 42 are shown in FIG. 43. The gate insulation films 10 are formed to surround the respective gate electrodes 11. Application of a predetermined potential to the gate electrodes 11 inverts the conductivity type of part of the p-type base region 8 adjacent to the gate insulation films 10 to form a channel between the n-type emitter regions 9 and the n-type base layer 1.
As illustrated in FIG. 43, the current path (a) includes the emitter electrode 19, the p-type semiconductor region 12, the p-type base region 8, the n-type base layer 1, the n-type buffer layer 3, the n-type cathode region 6, and the collector electrode 5. The current path (b) includes the collector electrode 5, the p-type collector layer 4, the n-type buffer layer 3, the n-type base layer 1, the p-type base region 8, the n-type emitter region 9, and the emitter electrode 19.
Thus, two IGBT structures are arranged in parallel along the current path (b), and a free-wheeling diode parasitic upon the IGBT is present along the current path (a). Although the structure for constituting the current path (a) and the structure for constituting the current path (b) are shown separately for purposes of illustration in FIG. 43, both of the structures are common for the most part.
The operation of the IGBT 90 is described below. When a negative voltage is applied to the collector terminal C, a pn junction comprised of the p-type collector layer 4 and the n-type buffer layer 3 does not allow current to flow along the current path (b), but current flows along the current path (a) to bring about a diode operation.
However since the collector electrode 5, the n-type buffer layer 3, the n-type base layer 1 and the emitter-side structure 2 are common to the current paths (a) and (b), when a positive voltage is applied to the collector terminal C, a current path (c) extending from the collector electrode 5 through the n-type cathode region 6 to the n-type buffer layer 3 is formed to increase the potential of the n-type buffer layer 3, making it difficult for a voltage Vx between the n-type buffer layer 3 and the p-type collector layer 4 to reach a voltage high enough to cause conductivity modulation. As a result, the IGBT so constructed does not act as an IGBT but acts as a MOS field effect transistor (MOS transistor).
To avoid such an erroneous action, it is necessary to decrease the area of the n-type cathode region 6 and part of the n-type buffer layer 3 which constitute the free wheeling diode and to increase the area of the p-type collector layer 4, thereby decreasing a current ix flowing through a resistor Rx.
However, the decrease in the area of the n-type cathode region 6 (and the part of the n-type buffer layer 3) increases a forward voltage Vf of the free wheeling diode during the operation of the constituents of the current path (a), i.e., the free wheeling diode, and causes an on-state current and a recovery current of the free wheeling diode to concentrate on the n-type cathode region 6 (and the part of the n-type buffer layer 3) to increase a current density, which might result in device breakdown.
The background art inverter has been constructed such that two separately formed devices, i.e. the IGBT and the free wheeling diode, are arranged in parallel or such that the free wheeling diode is incorporated in the IGBT. The former has the disadvantage of increasing the module area of the inverter. The latter is disadvantageous in that turning on the IGBT requires as small the area of the n-type cathode region 6 as possible for suppression of the increase in potential of the n-type buffer layer 3, resulting in a strong likelihood of the device breakdown due to current concentration during the operation of the free wheeling diode.
According to a first aspect of the present invention, a power semiconductor device comprises: a first semiconductor layer of a first conductivity type; an assembly of units including a first semiconductor region of a second conductivity type selectively formed in a first main surface of the first semiconductor layer, a second semiconductor region of the first conductivity type selectively formed in a surface of the first semiconductor region, a gate insulation film formed in contact with at least the surface of the first semiconductor region between the second semiconductor region and the first semiconductor layer, and a gate electrode formed on the gate insulation film; a first main electrode formed in contact with at least the second semiconductor region; a second semiconductor layer of the second conductivity type selectively formed in a second main surface of the first semiconductor layer in corresponding relation to a region in which the assembly of units is formed; a second main electrode formed in contact with a surface of the second semiconductor layer; and a current suppressing device for suppressing a main current flowing into the first semiconductor layer around the second semiconductor layer under a predetermined condition when a voltage is applied to the gate electrode so as to form a channel in the first semiconductor region.
Preferably, according to a second aspect of the present invention, in the power semiconductor device of the first aspect, the current suppressing device includes a pn junction diode, the pn junction diode including a second conductivity type semiconductor layer electrically connected to the first semiconductor layer around the second semiconductor layer, and a first conductivity type semiconductor layer electrically connected to the second main electrode. The predetermined condition includes a condition that a voltage applied to the second main electrode is greater than a voltage applied to the first main electrode.
Preferably, according to a third aspect of the present invention, in the power semiconductor device of the second aspect, the pn junction diode includes: a second conductivity type semiconductor layer formed on a region in which the first semiconductor layer around the second semiconductor layer is formed; and a first conductivity type semiconductor layer formed on at least the second conductivity type semiconductor layer.
Preferably, according to a fourth aspect of the present invention, in the power semiconductor device of the first aspect, the current suppressing device includes a Schottky diode, the Schottky diode including: a semiconductor layer of the second conductivity type formed on a metal electrode formed on the first semiconductor layer around the second semiconductor layer; and a metal layer formed in contact with the second main electrode and the semiconductor layer, the metal layer being made of a material for Schottky connection to the semiconductor layer. The predetermined condition includes a condition that a voltage applied to the second main electrode is greater than a voltage applied to the first main electrode.
Preferably, according to a fifth aspect of the present invention, in the power semiconductor device of the first aspect, the current suppressing device includes a Schottky diode, the Schottky diode including: a semiconductor layer of the second conductivity type formed on a metal electrode formed on the first semiconductor layer around the second semiconductor layer; and a metal layer, the metal layer being used also as the second main electrode, the metal layer being formed in contact with the second semiconductor layer and the semiconductor layer, the metal layer being made of a material for ohmic connection to the second semiconductor layer and for Schottky connection to the semiconductor layer. The predetermined condition includes a condition that a voltage applied to the second main electrode is greater than a voltage applied to the first main electrode.
Preferably, according to a sixth aspect of the present invention, in the power semiconductor device of the fifth aspect, the semiconductor layer is made of a semiconductor material having a greater electron affinity than silicon.
Preferably, according to a seventh aspect of the present invention, in the power semiconductor device of the first aspect, the current suppressing device includes a MOS transistor, the MOS transistor including a gate electrode, a first main electrode electrically connected to the first semiconductor layer around the second semiconductor layer, and a second main electrode electrically connected to the second main electrode. A voltage applied to the gate electrode and a voltage applied to the gate electrode of the MOS transistor complementarily turn on the gate electrode and the gate electrode of the MOS transistor.
Preferably, according to an eighth aspect of the present invention, the power semiconductor device of the first aspect further comprises: a first lifetime setting region formed in a region extending in a direction of the thickness of the first semiconductor layer from a region in which the first semiconductor layer around the second semiconductor layer is formed; and a second lifetime setting region formed in the first semiconductor layer adjacent the second semiconductor layer in corresponding relation to a region in which the second semiconductor layer is formed, wherein a carrier lifetime in the first and second lifetime setting regions is shorter than a carrier lifetime in the first semiconductor layer.
Preferably, according to a ninth aspect of the present invention, in the power semiconductor device of the eighth aspect, the carrier lifetime in the second lifetime setting region is shorter than that in the first lifetime setting region.
According to a tenth aspect of the present invention, a power semiconductor device comprises: a first semiconductor layer of a first conductivity type; a first assembly of units including a first semiconductor region of a second conductivity type selectively formed in a first main surface of the first semiconductor layer, a second semiconductor region of the first conductivity type selectively formed in a surface of the first semiconductor region, a first gate insulation film formed in contact with at least the surface of the first semiconductor region between the second semiconductor region and the first semiconductor layer, and a first gate electrode formed on the first gate insulation film; a second assembly of units including a third semiconductor region of the second conductivity type selectively formed in a second main surface of the first semiconductor layer, a fourth semiconductor region of the first conductivity type selectively formed in a surface of the third semiconductor region, a second gate insulation film formed in contact with at least the surface of the third semiconductor region between the fourth semiconductor region and the first semiconductor layer, and a second gate electrode formed on the second gate insulation film; a first main electrode formed in contact with at least the second semiconductor region; and a second main electrode formed in contact with at least the fourth semiconductor region.
Preferably, according to an eleventh aspect of the present invention, the power semiconductor device of the tenth aspect further comprises a lifetime setting region positioned closer to the second assembly of units than the middle of the thickness of the first semiconductor layer and having a width corresponding to at least the width of a region in which the first and second assemblies of units are formed, wherein a carrier lifetime in the lifetime setting region is shorter than a carrier lifetime in the first semiconductor layer.
Preferably, according to a twelfth aspect of the present invention, in the power semiconductor device of the eleventh aspect, the first semiconductor layer is divided into a first part closer to the first assembly of units and a second part closer to the second assembly of units, and the first and second parts are different from each other in at least one of crystal plane orientation and crystal axis orientation. The lifetime setting region serves as a boundary region between the first and second parts of the first semiconductor layer.
Preferably, according to a thirteenth aspect of the present invention, in the power semiconductor device of the tenth aspect, the first semiconductor layer is divided into a first part extending from a predetermined position closer to the second assembly of units than the middle of the thickness of the first semiconductor layer to the second assembly of units and a second part closer to the first assembly of units, and a carrier lifetime in the first part is shorter than a carrier lifetime in the second part.
Preferably, according to a fourteenth aspect of the present invention, the power semiconductor device of the tenth aspect further comprises one of a metal layer and a third semiconductor layer of the first conductivity type which are positioned closer to the second assembly of units than the middle of the thickness of the first semiconductor layer and which have a width corresponding to at least the width of a region in which the first and second assemblies of units are formed, the third semiconductor layer being higher in concentration than the first semiconductor layer.
According to a fifteenth aspect of the present invention, a power semiconductor device comprises: a first conductivity type semiconductor layer; a second conductivity type semiconductor layer selectively formed in a first main surface of the first conductivity type semiconductor layer; first electric field relieving means for relieving an electric field in the first conductivity type semiconductor layer around the second conductivity type semiconductor layer; an electrode layer selectively formed on a second main surface of the first conductivity type semiconductor layer; and second electric field relieving means for relieving an electric field in the first conductivity type semiconductor layer outside the electrode layer.
Preferably, according to a sixteenth aspect of the present invention, the power semiconductor device of the fifteenth aspect further comprises: a first semiconductor region of a first conductivity type selectively formed in the first main surface of the first conductivity type semiconductor layer outside the first electric field relieving means; a second semiconductor region of the first conductivity type selectively formed in the second main surface of the first conductivity type semiconductor layer outside the second electric field relieving means; and a third semiconductor region of the first conductivity type selectively formed on a side surface of the first conductivity type semiconductor layer.
Preferably, according to a seventeenth aspect of the present invention, in the power semiconductor device of the sixteenth aspect, the first electric field relieving means includes a plurality of first ring regions of a second conductivity type arranged concentrically in ring-like form in the first main surface of the first conductivity type semiconductor layer. The second electric field relieving means includes a plurality of second ring regions of the second conductivity type arranged concentrically in ring-like form in the second main surface of the first conductivity type semiconductor layer. The plurality of first ring regions and the plurality of second ring regions are spaced at outwardly increasing intervals.
An eighteenth aspect of the present invention is intended for a method of manufacturing a power semiconductor device. According to the present invention, the method comprises the steps of: (a) forming a first assembly of units, the step (a) including the steps of preparing a first semiconductor substrate of a first conductivity type, selectively forming a first semiconductor region of a second conductivity type in a first main surface of the first semiconductor substrate, selectively forming a second, semiconductor region of the first conductivity type in a surface of the first semiconductor region, forming a first gate insulation film in contact with at least the surface of the first semiconductor region between the second semiconductor region and the first semiconductor substrate, and forming a first gate electrode on the first gate insulation film; (b) forming a second assembly of units, the step (b) including the steps of preparing a second semiconductor substrate of the first conductivity type, selectively forming a third semiconductor region of the second conductivity type in a first main surface of the second semiconductor substrate, selectively forming a fourth semiconductor region of the first conductivity type in a surface of the third semiconductor region, forming a second gate insulation film in contact with at least the surface of the third semiconductor region between the fourth semiconductor region and the second semiconductor substrate, and forming a second gate electrode on the second gate insulation film; and (c) joining a second main surface of the first semiconductor substrate and a second main surface of the second semiconductor substrate together by a bonding technique.
A nineteenth aspect of the present invention is also intended for a method of manufacturing a power semiconductor device. According to the present invention, the method comprises the steps of: (a) preparing a first semiconductor substrate of a first conductivity type, selectively forming a second conductivity type semiconductor layer in a first main surface of the first semiconductor substrate, and forming first electric field relieving means for relieving an electric field in the first semiconductor substrate around the second conductivity type semiconductor layer; (b) preparing a second semiconductor substrate of the first conductivity type, and forming second electric field relieving means for relieving an electric field in the second semiconductor substrate outside an electrode layer to be formed on a first main surface of the second semiconductor substrate; and (c) joining a second main surface of the first semiconductor substrate and a second main surface of the second semiconductor substrate together by a bonding technique.
In accordance with the first aspect of the present invention, the power semiconductor device comprises the current suppressing device for suppressing the main current flowing into the first semiconductor layer around the second semiconductor layer under the predetermined condition. The power semiconductor device designed to incorporate therein a free wheeling diode including the first semiconductor region and the first semiconductor layer can suppress the main current flowing from the second main electrode into the first semiconductor layer during the operation of an IGBT including the gate electrode, the gate insulation film, the second semiconductor region, the first semiconductor region, the first semiconductor layer and the second semiconductor layer, to prevent the increase in potential of the first semiconductor layer for the operation of the IGBT. Further, the connection of the current suppressing device eliminates the need to reduce the area of the first semiconductor layer around the second semiconductor layer, thereby preventing device breakdown due to current concentration during the operation of the free wheeling diode.
In accordance with the second aspect of the present invention, the power semiconductor device uses the pn junction diode as the current suppressing device. This suppresses the main current flowing from the second main electrode into the first semiconductor layer when the voltage applied to the second main electrode is greater than the voltage applied to the first main electrode during the operation of the IGBT, to prevent the increase in the potential of the first semiconductor layer for the operation of the IGBT.
In accordance with the third aspect of the present invention, the power semiconductor device employs the incorporated pn junction diode to reduce a device area as compared with a power semiconductor device employing a separately provided diode.
In accordance with the fourth aspect of the present invention, the power semiconductor device uses the Schottky diode as the current suppressing device, to require the semiconductor layers the number of which is less by one than that employing the pn junction diode. This simplifies a method of manufacturing the power semiconductor device and reduces manufacturing costs.
In the power semiconductor device in accordance with the fifth aspect of the present invention, the second main electrode is used also as the metal layer of the Schottky diode. This further simplifies the construction and the manufacturing method thereof and further reduces the manufacturing costs.
In the power semiconductor device in accordance with the sixth aspect of the present invention, the semiconductor layer of the Schottky diode is made of the semiconductor material having a greater electron affinity than silicon to ensure the Schottky connection to the metal layer.
In accordance with the seventh aspect of the present invention, the power semiconductor device uses the MOS transistor as the current suppressing device and makes the setting so that the gate electrode and the gate electrode of the MOS transistor operate complementarily. Thus, the power semiconductor device can suppress the main current flowing from the second main electrode into the first semiconductor layer when the voltage which turns on the gate electrode is applied thereto, to prevent the increase in the potential of the first semiconductor layer for operation of the IGBT.
In the power semiconductor device in accordance with the eighth aspect of the present invention, the first lifetime setting region is a region on which the current paths of the free wheeling diode of the respective units are concentrated, and the second lifetime setting region is a region included in the current paths of the IGBT of the respective units. Therefore, the total power consumption is optimized which is the sum of the power consumption during the IGBT operation and the power consumption during the diode operation.
In the semiconductor device according to the ninth aspect of the present invention, a substantially optimum carrier lifetime distribution may be set independently for the IGBT and the free wheeling diode incorporated therein.
In accordance with the tenth aspect of the present invention, the power semiconductor device may have a structure incorporating therein the IGBT and the free wheeling diode by applying complementary signals to the first and second gate electrodes, and allows the completely independent operations of the IGBT and the free wheeling diode. This eliminates the problem that the presence of the free wheeling diode does not cause the IGBT operation but causes the MOS transistor operation.
In the power semiconductor device in accordance with the eleventh aspect of the present invention, the presence of the lifetime setting region having a shorter carrier lifetime than the first semiconductor layer suppresses the injection of holes from the collector during the operation of the IGBT to reduce energy dissipation caused by switching.
In accordance with the twelfth aspect of the present invention, the power semiconductor device achieves a simple and convenient structure for providing the lifetime setting region.
In the power semiconductor device in accordance with the thirteenth aspect of the present invention, when the power semiconductor device acts as the IGBT, the presence of the part of the first semiconductor layer which is closer to the second assembly of units and has a shorter carrier lifetime suppresses the injection of holes from the collector during the IGBT operation, to reduce the energy dissipation caused by switching.
In the power semiconductor device in accordance with the fourteenth aspect of the present invention, when the power semiconductor device acts as the IGBT, the presence of the metal layer or the third semiconductor layer decreases an on-state voltage.
In the power semiconductor device in accordance with the fifteenth aspect of the present invention, the presence of the second electric field relieving means decreases the voltage applied to the first electric field relieving means to reduce the size of the region in which the first electric field relieving means is formed. This accomplishes the reduction in size and costs of the power semiconductor device.
In the power semiconductor device in accordance with the sixteenth aspect of the present invention, the presence of the first to third semiconductor regions completely prevents a depletion layer from extending to the side surface of the substrate.
In accordance with the seventeenth aspect of the present invention, the power semiconductor device can efficiently relieve the electric field.
In accordance with the eighteenth aspect of the present invention, the method provides the power semiconductor device of the twelfth aspect in simple and reliable manner.
In accordance with the nineteenth aspect of the present invention, the method provides the power semiconductor device of the fifteenth aspect in simple and reliable manner.
It is therefore an object of the present invention to provide a power semiconductor device including an IGBT and a free wheeling diode, which is reduced in size and which prevents device breakdown due to current concentration during the operation of the free wheeling diode incorporated in the IGBT.